源代码
module trigger(
input wire clk ,
input wire T ,
output wire Q3
);
reg Q1,q1;
reg Q2,q2;
reg R,D,J,K;
reg reg_Q3,q3;
reg reg_T;
assign T= reg_T;
assign Q3 = reg_Q3;
always @ (posedge clk)
begin
Q1<=(reg_T&(Q1))|((reg_T)&Q1);
q1<=((reg_T&(Q1))|((reg_T)&Q1));D;
D<=Q1;
K<=q1;
end
always @ (negedge clk)
begin
Q2<=D;
q2<=
J<=Q2;
end
always @ (negedge clk)
begin
reg_Q3<=(J&(reg_Q3))|((K)®_Q3);
q3<=((J&(reg_Q3))|((~K)®_Q3));
R<=q2&q3;
end
endmodule
测试代码
`timescale 1ns/1ps
module tb_trigger();
reg T,clk;
wire Q3;
initial begin
T=1'b1;
clk=1'b0;
end
always #10 clk=~clk;
trigger tb_trigger(
.T(T),
.clk(clk),
.Q3(Q3)
);
endmodule