verilog写一个32位并转串的模块请帮我看看哪里错了

Question

module BZHUANCHUAN(CLK_RCK,CLK_SCK,BING_IN,CHUAN_OUT);
input CLK_RCK,CLK_SCK;
input [0:31]BING_IN;
output CHUAN_OUT;
reg [0:31]store;

always@(posedge CLK_RCK)
begin
store<=BING_IN;
for(i=0;i<32;i++)
@(posedge CLK_SCK) CHUAN_OUT<=store(i);

end;

end module
第一个错误就是for(i=0;i<32;i++)这句它说

Error (10170): Verilog HDL syntax error at BZHUANCHUAN.v(11) near text "+"; expecting "="

Answer 1

是i没有配置寄存器么