用fpga控制带有寄存器的ad芯片进行spi传输

Question

求一些有利用fpga配置带有寄存器的ad转换芯片。有关于fpga如何对ad寄存器的地址操作进行spi传输的相关verilog代码及解释。

Answer 1

使用Spartan6控制AD9613进行采样，
module testmode_spi(

input clk_25,
input rst,

output reg csb,
output reg oeb,
output clk_spi,
output reg [7:0] state,
output write,
output reg [7:0] tr_delay,

//output reg [7:0] sdio_spi_id,

output reg fin_ad_reg,

inout sdio

);


reg     rd_wr   = 0;        //璇诲啓
parameter       phase   =   2'b00;      //w1鍜寃0

parameter       spi_syn =           {8'h3a,8'h01};



reg         wr_valid;
reg         [23:0]  sdio_data1;
reg         [23:0]  sdio_data2;

reg         sdio_out;
reg         [15:0]  sdio_rd;

// reg [7:0] sdio_spi_id;
// reg [7:0] state;

reg         [7:0]   id_cnt;
reg         [3:0]   num;

// reg [7:0] tr_delay;
reg write;
reg [15:0] cnt;
reg [23:0] sdio_data_te;

parameter   st_idle = 4'd0;
parameter   wr_cmd1 = 4'd1;
parameter   waite   = 4'd2;

// parameter wr_cmd3 = 4'd3;
// parameter wr_cmd4 = 4'd4;
// parameter wr_cmd5 = 4'd5;
parameter rd_delay = 4'd6;
parameter rd_cmd1 = 4'd7;
parameter rd_cmd2 = 4'd8;
parameter re_delay = 4'd9;

parameter   w2r_delay   =   5000;


assign sdio = write ? sdio_out:1'bz;
assign clk_spi = ~clk_25;

always @(posedge clk_25)
    if(!rst)
        wr_valid <= 0;
    else if(state == wr_cmd1)
        wr_valid <= 1;
    else 
        wr_valid <= wr_valid;






always @(posedge clk_25)begin
    if(!rst)begin
        state <= st_idle;
        sdio_data1 <= 0;
        sdio_data2 <= 0;

        sdio_rd <= 0;


        waite : begin
            state <= waite;
            fin_ad_reg <= 1;
        end


        default :state <= st_idle;
        endcase
    end
end




always @(posedge clk_25)
    if(!rst)
        num <= 0;
    else if(state == wr_cmd1)
        num <= 1;
    else if(state == waite)
        num <= 2;

    else 
        num <= num;

always @(posedge clk_25)
    if(!rst)
        tr_delay <= 0;
    else if(num == 2 && tr_delay <= 30)
        tr_delay <= tr_delay + 1;

    else
        tr_delay <= 0;


always @(posedge clk_25)
    if(!rst)
        csb <= 1;
    else if(tr_delay > 2 && tr_delay <= 26 && num == 2 )
        csb <= 0;                       

        csb <= 1;

always @(posedge clk_25 )
    if(!rst)
        sdio_out <= 0;
    else if(num == 2 && tr_delay > 2)
        sdio_out <= sdio_data1['d26-tr_delay];

    else 
        sdio_out <= 0;

always @(posedge clk_25)
    if(!rst)
        oeb <= 1;
    else if(num >= 2)
        oeb <= 0;
    else 
        oeb <= 1;

endmodule