reg [7:0] din_r;
assign led = din;
reg [2:0] state;/eck serial 5'b1_1010
always @ (posedge clk or negedge rst_n)
if (!rst_n) begin
flag <= 1'b0;
din_r <= din;
state <= 'd0;
end
else if(!en) begin
case (state):
'd0 :
begin
flag <= 1'b0;
din_r <= {din_r[6:0],1'b1};
if (din_r[7]==1'b0)//被检测数据的最高位和0相比,是否相等
state <= 'd1;
else
state <= 'd0;
end
'd1 :
begin
flag <= 1'b0;
din_r <={din_r[6:0],1'b1};
if (din_r[7] == 1'b0)
state <= 'd1;
else
state <= 'd0;
end
'd2 :
begin
flag <= 1'b0;
din_r <={din_r[6:0],1'b1};
if (din_r[7] == 1'b0)
state <= 'd2;
else
state <= 'd0;
end
'd3 :
begin
flag <= 1'b0;
din_r <={din_r[6:0],1'b1};
if (din_r[7] == 1'b0)
state <= 'd4;
else
state <= 'd0;
end
'd4 :
begin
if (din_r[7] == 1'b0)
flage <= 1'b1;
end
default :
begin
state <= 'd0;
flag <= 1'b0;
end
endcase
end
endmodule