最近使用到Axi4_Stream Data Fifo这个IP时遇到了一个问题，欢迎各位前来讨论讨论是哪的问题？
具体问题是 IP手册上面写的是开启 Packet模式后，直到tlast信号拉高或者Fifo满时Master接口开始送出数据，而我在使用过程中的现象是fifo满后才开始通过master信号发送数据，Slave接口的tlast信号拉高并不能开启Master接口进行传数据的输出，而对这个IP的模板工程进行仿真却是正确的，不知给我仿真代码的问题还是什么问题？下面放了我的仿真代码和波形图还有模板工程的仿真波形图
IP手册连接：https://china.xilinx.com/conten
仿真波形
仿真代码：
`timescale 1ns/1ps
module tb_fifo_top();
parameter PERIOD=10;
reg rst_n;
bit clk;
reg s_axis_tvalid;
wire s_axis_tready;
reg [31:0]s_axis_tdata;
reg [3:0] s_axis_tkeep;
reg s_axis_tlast;
wire m_axis_tvalid;
reg m_axis_tready;
wire [31:0] m_axis_tdata;
wire [3:0] m_axis_tkeep;
wire m_axis_tlast;
always #(PERIOD/2) clk=~clk;
initial begin
rst_n=0;
#PERIOD;
rst_n=1;
s_axis_tlast=0;
generate_fifo_data(600);
#500;
generate_fifo_data(400);
#300;
m_axis_tready=1;
generate_fifo_data(300);
end
integer i;
task generate_fifo_data(input int unsigned number);
begin
s_axis_tkeep=4'hf;
for(i=0;i<number;i++)begin
@(posedge clk);
s_axis_tvalid=1;
s_axis_tdata=($random)%20;
while(~(s_axis_tvalid&&s_axis_tready))@(posedge clk);
end
s_axis_tdata=($random)%10;
s_axis_tlast=1;
@(posedge clk);
s_axis_tlast=0;
s_axis_tvalid=0;
end
endtask
fifo_top u_fifo_top(
.rst_n (rst_n ),
.clk (clk ),
.s_axis_tvalid (s_axis_tvalid ),
.s_axis_tready (s_axis_tready ),
.s_axis_tdata (s_axis_tdata ),
.s_axis_tkeep (s_axis_tkeep ),
.s_axis_tlast (s_axis_tlast ),
.m_axis_tvalid (m_axis_tvalid ),
.m_axis_tready (m_axis_tready ),
.m_axis_tdata (m_axis_tdata ),
.m_axis_tkeep (m_axis_tkeep ),
.m_axis_tlast (m_axis_tlast )
);
endmodule
模板工程仿真波形图：
