问题遇到的现象和发生背景
我想在vivado中完成zynq->AXI DMA->AXI stream data FIFO->BRAM的数据传输,但是FIFO输出数据是AXI-stream格式,BRAM控制器只能接受AXI memory map数据,所以需要转换一下。我现在想到的是在FIFO和BRAM之间再放一个AXI DMA,但是搭完block design之后有报错。DMA似乎只能用在PS和PL之间传输数据,而不能用在FIFO和BRAM controller之间。有没有其他的解决方法呢?
block design截图
运行结果及报错内容
[BD 41-703] Slave segment </axi_bram_ctrl_0/S_AXI/Mem0> is mapped into master segment </processing_system7_0/Data/SEG_axi_bram_ctrl_0_Mem0>, but there is no path between them. Please delete the master segment or check your design to ensure a valid path can be created.