Verilog 宏定义怎么用？

Question

我用define定义了两个数，系统一直报错，未定义

`timescale 1ns/1ps

`define    SS     32'd49999999
`define    DD     32'd50000000

module LED
(
    clk,
    rst_n,
    led
);

input clk;
input rst_n;
output[3:0] led;

reg[31:0] timer;
reg[3:0] led;

always@(posedge clk or negedge rst_n)
begin 
    if(~rst_n)
        timer<=0;
    else if(timer == SS+5*DD)
        timer<=0;
    else
        timer<=timer+1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        led<=4'b1111;
    else if(timer==SS)
        led<=4'b1110;
    else if((timer==SS+DD)|(timer==SS+5*DD))
        led<=4'b1101;
    else if((timer==SS+2*DD)|(timer==SS+4*DD))
        led<=4'b1011;
    else if(timer==SS+3*DD)
        led<=4'b0111;
end

endmodule

我把define这两句放到module中间定义也不对，这是因为啥原因？

Answer 1

用的时候要加 “·”

`timescale 1ns/1ps
 
`define    SS     32'd49999999
`define    DD     32'd50000000
 
module LED
(
    clk,
    rst_n,
    led
);
 
input clk;
input rst_n;
output[3:0] led;
 
reg[31:0] timer;
reg[3:0] led;
 
always@(posedge clk or negedge rst_n)
begin 
    if(~rst_n)
        timer<=0;
    else if(timer == `SS+5*`DD)
        timer<=0;
    else
        timer<=timer+1'b1;
end
 
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        led<=4'b1111;
    else if(timer==`SS)
        led<=4'b1110;
    else if((timer==`SS+`DD)|(timer==`SS+5*`DD))
        led<=4'b1101;
    else if((timer==`SS+2*`DD)|(timer==`SS+4*`DD))
        led<=4'b1011;
    else if(timer==`SS+3*`DD)
        led<=4'b0111;
end
 
endmodule