在Verilog中用always来编写程序
always @(posedge clk,negedge rst_n)begin
if( rst_n==0 )
begin
state <= s01;
led <= 1'b1;
end
else
if (flag2 == 1'b1)
begin
state <= s00;
led <= 1'b0;
end
else
if (flag3 == 1'b1)
begin
state <= s01;
led <= 1'b1;
end
//assign led = (flag3 == 1'b1)?1'b0:1'b1;
//assign led = (flag2 == 1'b1)?1'b1:1'b0;
//assign led = (rst_n == 0)?1'b1:1'b0;
end
endmodule
仿真如中输出的led为00和01,如果想要显示为0或者1,就要用assign来输出led,但是在这段里面assign无论如何都插入不进去,就是那三行注释部分,只是不知道放哪所以放在那,想问一下有没有办法把那三行放进去或者是说还有别的方法可以输出只显示0和1