Vivado 2019.1仿真verilog报错[USF-XSim-62]和[Vivado 12-4473]，疑似仿真代码没有正确调用模块？

Question

下面是源文件

module Ex_1(
    input [23:0] sw,
    output [23:0] led
    );
   assign led =sw;
endmodule

仿真代码

`timescale 1ns / 1ps
module Ex_1_sim( );
    reg [23:0] sw=24'h000000;
    wire [23:0] led;
    Ex_1 uut(
        .sw(sw),
        .led(led)
        );
always #10 sw=sw+1;
endmodule

报错信息：
[USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/yx/Desktop/JIZU/Ex_1/Ex_1.sim/sim_1/behav/xsim/elaborate.log' file for more information.

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

错误日志：
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/Ex_1_sim_behav/obj/xsim_1.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...

求解答

Answer 1

https://blog.csdn.net/LANHUAMANJIANGHONG/article/details/77865768