问题遇到的现象和发生背景
问题相关代码,请勿粘贴截图
module elock(clk,k1,k2,k3,k4,k5,k6,k7,k8,k9,Rst,ledsel,leddata);
input clk,k1,k2,k3,k4,k5,k6,k7,k8,k9,Rst;
output ledsel;
output [7:0] leddata;
reg [7:0] leddata;
reg [1:0] count;
reg [3:0] count1;
reg [2:0] state,next_state;
reg en,carry_out,op,error;
reg k11,k22,k33,k44,k55,k66,k77,k88,k99,rst;
assign ledsel=1'b1;
always@(posedge clk)
begin
if(k1==1'b1)
k11<=1'b1;
else
k11<=1'b0;
if(k2==1'b1)
k22<=1'b1;
else
k22<=1'b0;
if(k3==1'b1)
k33<=1'b1;
else
k33<=1'b0;
if(k4==1'b1)
k44<=1'b1;
else
k44<=1'b0;
if(k5==1'b1)
k55<=1'b1;
else
k55<=1'b0;
if(k6==1'b1)
k66<=1'b1;
else
k66<=1'b0;
if(k7==1'b1)
k77<=1'b1;
else
k77<=1'b0;
if(k8==1'b1)
k88<=1'b1;
else
k88<=1'b0;
if(k9==1'b1)
k99<=1'b1;
else
k99<=1'b0;
if(Rst==1'b1)
rst<=1'b1;
else
rst<=1'b0;
end
always@(posedge clk)
begin
state<=next_state;
end
always@(state,en,k11,k22,k33,k44,k55,k66,k77,k88,k99,rst)
begin
if(rst)
begin
next_state<=3'b000;
op<=1'b0;
end
case(state)
3'b000:begin
if(k11&en)
next_state<=3'b001;
else //if((k22|k33|k44|k55|k66|k77|k88|k99))
//error<=1'b1;
//else
next_state<=3'b000;
end
3'b001:begin
if(k99&en)
next_state<=3'b010;
else //if((k11|k22|k33|k44|k55|k66|k77|k88))
// error<=1'b1;
//else
next_state<=3'b001;
end
3'b010:begin
if(k88&en)
next_state<=3'b011;
else //if((k11|k22|k33|k44|k55|k66|k77|k99))
// error<=1'b1;
//else
next_state<=3'b010;
end
3'b011:begin
if(k88&en)
next_state<=3'b100;
else// if((k11|k22|k33|k44|k55|k66|k77|k99))
// error<=1'b1;
//else
next_state<=3'b011;
end
3'b100:begin
if(k33&en)
next_state<=3'b101;
else //if((k11|k22|k44|k55|k66|k77|k88|k99))
// error<=1'b1;
// else
next_state<=3'b100;
end
3'b101:op<=1'b1;
default:next_state<=3'b000;
endcase
end
always@(posedge clk)
begin
if(rst)
count1<=4'b0000;
else if(op==1'b1)
count1<=4'b1111;
else if(en==1'b0)
count1<=4'b1110;
else if(en&(k11|k22|k33|k44|k55|k66|k77|k88|k99))
count1<=count1+4'b0001;
end
always@(count1)
if(count1<=4'b0101)
en<=1'b1;
else
en<=1'b0;
always@(count1)
case(count1)
4'd0:leddata<=~8'b11000000;
4'd1:leddata<=~8'b11111001;
4'd2:leddata<=~8'b10100100;
4'd3:leddata<=~8'b10110000;
4'd4:leddata<=~8'b10011001;
4'd5:leddata<=~8'b10010010;
4'd6:leddata<=~8'b10000011;
4'd7:leddata<=~8'b11111000;
4'd8:leddata<=~8'b10000000;
4'd9:leddata<=~8'b10011000;
4'b1111:leddata<=8'b0111_0011;
4'b1110:leddata<=8'b0111_1001;
default:leddata<=~8'b11000000;
endcase
endmodule
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