kotaerop 2021-07-11 16:14 采纳率: 0%

# verilog 简易数字时钟 代码的疑惑

``````module wjt1(
input clk,
input rst,
input sw,

output reg [10:0] display_out

//output reg [3:0] an
);

reg [3:0]second1,min1;
reg [3:0]second2,min2,hour1,hour2;
reg cy_1,cy_2,cy_3,cy_4,cy_5;
reg [1:0] k;
reg clk1hz,clk20ms;
reg [23:0]counter1;
reg [31:0]counter2;
reg k1,k2,k3,k4;
reg [3:0]d;
reg set1;
reg [3:0] second11,second21,min11,min21;

always @ (posedge clk1hz or  negedge rst )
begin
if(rst)begin
second1=0;second2=0;
cy_1=0;cy_2=0;
end
else begin
if((second2<4'b0101)&(second1==4'b1001))   begin second1=0;cy_1=1;end else begin second1=second1+1;cy_1=0;end
if((second2==4'b0101)&(second1==4'b1001))  begin second1<=0;second2<=0;cy_2=1;end  else cy_2=0;

if(cy_1) second2=second2+1;
end
end

always @ (posedge clk1hz or  negedge rst )
begin
if(rst)begin
min1=0;min2=0;
cy_3=0;cy_4=0;
end
else  begin
if((min2<4'b0101)&(min1==4'b1001)&cy_2)   begin min1=0;cy_3=1;end else begin if(cy_2) min1=min1+1;cy_3=0;end
if((min2==4'b0101)&(min1==4'b1001)&cy_2)  begin min1<=0;min2<=0;cy_4=1;end  else cy_4=0;

if(cy_3&cy_2) min2=min2+1;
end
end

always @ (posedge clk1hz or  negedge rst )
begin
if(rst)begin
hour1=0;hour2=0;
cy_5=0;cy_4=0;
end
else  begin
if((hour2<4'b0010)&(hour1==4'b1001)&cy_4)   begin hour1=0;cy_5=1;end else begin if(cy_4) hour1=hour1+1;cy_5=0;end
if((hour2==4'b0010)&(hour1==4'b0011)&cy_4)  begin hour1<=0;hour2<=0;end

if(cy_5&cy_4) hour2=hour2+1;
end
end

always @(posedge clk )
begin
if(rst) begin
clk1hz=0;
clk20ms=0;
counter1=0;
counter2=0;
end
else begin
if(counter1<250000) counter1=counter1+1;
else if(counter1==250000) begin counter1=0;clk20ms=!clk20ms;end
if(counter2<50000000) counter2=counter2+1;
else if(counter2==50000000)begin counter2=0;clk1hz=!clk1hz;end
end

end

always @(posedge clk20ms)
begin
if(rst) begin k=0;end
else begin
if(k<3) k=k+1;
else k=0;
end
end

always @(posedge clk20ms)
begin
if(rst) begin
second11=0;
second21=0;
min11=0;
min21=0;
end
else begin
second11=second1;
second21=second2;
min11=min1;
min21=min2;
end

end

always @(posedge clk20ms)
begin
if(rst)  display_out=11'b1111_1111111;
else  if(!sw)begin
case(k)
2'b00:
case(second1)
4'b0000: display_out=11'b1110_0000001;
4'b0001: display_out=11'b1110_1001111;
4'b0010: display_out=11'b1110_0010010;
4'b0011: display_out=11'b1110_0000110;
4'b0100: display_out=11'b1110_1001100;
4'b0101: display_out=11'b1110_0100100;
4'b0110: display_out=11'b1110_0100000;
4'b0111: display_out=11'b1110_0001111;
4'b1000: display_out=11'b1110_0000000;
4'b1001: display_out=11'b1110_0000100;
default: display_out=11'b1111_1111111;
endcase
2'b01:
case(second2)
4'b0000: display_out=11'b1101_0000001;
4'b0001: display_out=11'b1101_1001111;
4'b0010: display_out=11'b1101_0010010;
4'b0011: display_out=11'b1101_0000110;
4'b0100: display_out=11'b1101_1001100;
4'b0101: display_out=11'b1101_0100100;
4'b0110: display_out=11'b1101_0100000;
4'b0111: display_out=11'b1101_0001111;
4'b1000: display_out=11'b1101_0000000;
4'b1001: display_out=11'b1101_0000100;
default: display_out=11'b1111_1111111;
endcase
2'b10:
case(min1)
4'b0000: display_out=11'b1011_0000001;
4'b0001: display_out=11'b1011_1001111;
4'b0010: display_out=11'b1011_0010010;
4'b0011: display_out=11'b1011_0000110;
4'b0100: display_out=11'b1011_1001100;
4'b0101: display_out=11'b1011_0100100;
4'b0110: display_out=11'b1011_0100000;
4'b0111: display_out=11'b1011_0001111;
4'b1000: display_out=11'b1011_0000000;
4'b1001: display_out=11'b1011_0000100;
default: display_out=11'b1111_1111111;
endcase
2'b11:
case(min2)
4'b0000: display_out=11'b0111_0000001;
4'b0001: display_out=11'b0111_1001111;
4'b0010: display_out=11'b0111_0010010;
4'b0011: display_out=11'b0111_0000110;
4'b0100: display_out=11'b0111_1001100;
4'b0101: display_out=11'b0111_0100100;
4'b0110: display_out=11'b0111_0100000;
4'b0111: display_out=11'b0111_0001111;
4'b1000: display_out=11'b0111_0000000;
4'b1001: display_out=11'b0111_0000100;
default: display_out=11'b1111_1111111;
endcase
endcase
end
else begin
case(k)
2'b00:
case(min1)
4'b0000: display_out=11'b1110_0000001;
4'b0001: display_out=11'b1110_1001111;
4'b0010: display_out=11'b1110_0010010;
4'b0011: display_out=11'b1110_0000110;
4'b0100: display_out=11'b1110_1001100;
4'b0101: display_out=11'b1110_0100100;
4'b0110: display_out=11'b1110_0100000;
4'b0111: display_out=11'b1110_0001111;
4'b1000: display_out=11'b1110_0000000;
4'b1001: display_out=11'b1110_0000100;
default: display_out=11'b1111_1111111;
endcase
2'b01:
case(min2)
4'b0000: display_out=11'b1101_0000001;
4'b0001: display_out=11'b1101_1001111;
4'b0010: display_out=11'b1101_0010010;
4'b0011: display_out=11'b1101_0000110;
4'b0100: display_out=11'b1101_1001100;
4'b0101: display_out=11'b1101_0100100;
4'b0110: display_out=11'b1101_0100000;
4'b0111: display_out=11'b1101_0001111;
4'b1000: display_out=11'b1101_0000000;
4'b1001: display_out=11'b1101_0000100;
default: display_out=11'b1111_1111111;
endcase
2'b10:
case(hour1)
4'b0000: display_out=11'b1011_0000001;
4'b0001: display_out=11'b1011_1001111;
4'b0010: display_out=11'b1011_0010010;
4'b0011: display_out=11'b1011_0000110;
4'b0100: display_out=11'b1011_1001100;
4'b0101: display_out=11'b1011_0100100;
4'b0110: display_out=11'b1011_0100000;
4'b0111: display_out=11'b1011_0001111;
4'b1000: display_out=11'b1011_0000000;
4'b1001: display_out=11'b1011_0000100;
default: display_out=11'b1111_1111111;
endcase
2'b11:
case(hour2)
4'b0000: display_out=11'b0111_0000001;
4'b0001: display_out=11'b0111_1001111;
4'b0010: display_out=11'b0111_0010010;
4'b0011: display_out=11'b0111_0000110;
4'b0100: display_out=11'b0111_1001100;
4'b0101: display_out=11'b0111_0100100;
4'b0110: display_out=11'b0111_0100000;
4'b0111: display_out=11'b0111_0001111;
4'b1000: display_out=11'b0111_0000000;
4'b1001: display_out=11'b0111_0000100;
default: display_out=11'b1111_1111111;
endcase
endcase
end
end

endmodule

``````
• 写回答

#### 1条回答默认 最新

• 老皮芽子 2023-04-11 14:02
关注

= 堵塞赋值和 <=非堵塞赋值不要着用
在 always @(posedge clk20ms) 时序逻辑中尽量使用 <=非堵塞赋值

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• 创建了问题 7月11日

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