关于verilog中的population count

Question

module top_module(
input [254:0] in,
output [7:0] out );

always @(*) begin
    out = 0;
    for(int i = 0; i < 255; i++) begin
        if(in[i])
            out = out + 1;
        else
            out = out + 0;
    end
end

endmodule
这段代码在hdlbits（那个刷题的）上没有问题，但是在vivado和quartus上都有错误，都在for那一行错误为Error (10170): Verilog HDL syntax error at top_module.v(7) near text: "i"; expecting "=". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at top_module.v(7) near text: "<"; expecting "<=", or "=". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at <a href="https://www.altera.com/support/support-resources/knowledge-base/search.html" id="textarea_1659193290120_1659193514199_1">https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "top_module" at top_module.v(1) due to previous errors

Answer 1

module top_module(
input [254:0] in,
output [7:0] out );
integer    i;
always @(*) begin
    out = 0;
    for(i = 0; i < 255; i=i+1) begin
        if(in[i])
            out = out + 1;
        else
            out = out + 0;
    end
end
endmodule