问题遇到的现象和发生背景
问题相关代码,请勿粘贴截图
运行结果及报错内容
我的解答思路和尝试过的方法
`timescale 1ns / 1ps
//640*480@60Hz 25MHz
module vgatwo(
input clk,
input reset,
input [7:0]sw,
output [7:0]led,
output Hsync,//水平同步输出接口
output Vsync,//垂直同步输出接口
output reg [3:0]vgaRed, //输出的颜色值
output reg [3:0]vgaGreen, //输出的颜色值
output reg [3:0]vgaBlue //输出的颜色值
);
assign led=sw;
wire clk_vga;//对clk处理后的输出线
//调用ip核输出25MHz的时钟
clk_wiz_0 uut_clk
(
.clk_in1(clk),
.clk_out1(clk_vga)
);
parameter HPOLA = 0;
parameter VPOLA = 0;
parameter HTOTAL = 800; //scanline time
parameter HSYNCP = 96; //行同步信号
parameter HBACKP = 40; //
parameter LBORDER = 8; //消隐后沿
parameter HDISP = 640; //行显示
parameter RBORDER = 8; //
parameter HFRONTP = 8; //消隐前沿
//
parameter VTOTAL = 525; //scanline time
parameter VSYNCP = 2; //场同步信号
parameter VBACKP = 25; //
parameter TBORDER = 8; //消隐后沿
parameter VDISP = 480; //场显示
parameter BBORDER = 8; //
parameter VFRONTP = 2; //消隐前沿
reg [79:0] char[0:63];//16*5=80 80*32像素
reg [9:0] location_x = 280; //显示位置
reg [9:0] location_y = 208; //显示位置
initial
begin
//PM2.5
char[0] = 80'h0000_0000_0000_0000_0000;
char[1] = 80'h0000_0000_0000_0000_0000;
char[2] = 80'h0000_0000_0000_0000_0000;
char[3] = 80'h0000_0000_0000_0000_0000;
char[4] = 80'h0000_0000_0000_0000_0000;
char[5] = 80'h0000_0000_0000_0000_0000;
char[6] = 80'hFFF0_F00F_07E0_0000_0FFC;
char[7] = 80'h3C7C_381C_0838_0000_0FFC;
char[8] = 80'h3C1E_381C_1018_0000_1000;
char[9] = 80'h3C1E_381C_200C_0000_1000;
char[10] = 80'h3C0E_381C_200C_0000_1000;
char[11] = 80'h3C0E_382C_300C_0000_1000;
char[12] = 80'h3C0E_2C2C_300C_0000_1000;
char[13] = 80'h3C0E_2C2C_000C_0000_1000;
char[14] = 80'h3C1E_2C2C_0018_0000_13E0;
char[15] = 80'h3C1E_2C4C_0018_0000_1430;
char[16] = 80'h3C7C_2C4C_0030_0000_1818;
char[17] = 80'h3FF0_264C_0060_0000_1008;
char[18] = 80'h3C00_264C_00C0_0000_000C;
char[19] = 80'h3C00_264C_0180_0000_000C;
char[20] = 80'h3C00_268C_0300_0000_000C;
char[21] = 80'h3C00_228C_0200_0000_000C;
char[22] = 80'h3C00_238C_0404_0000_300C;
char[23] = 80'h3C00_238C_0804_0000_300C;
char[24] = 80'h3C00_230C_1004_1800_2018;
char[25] = 80'h3C00_230C_200C_3C00_2018;
char[26] = 80'h3C00_210C_3FF8_3C00_1830;
char[27] = 80'hFF00_F13F_3FF8_1800_07C0;
char[28] = 80'h0000_0000_0000_0000_0000;
char[29] = 80'h0000_0000_0000_0000_0000;
char[30] = 80'h0000_0000_0000_0000_0000;
char[31] = 80'h0000_0000_0000_0000_0000;
//CO2
char[32] = 80'h0000_0000_0000_0000_0000;
char[33] = 80'h0000_0000_0000_0000_0000;
char[34] = 80'h0000_0000_0000_0000_0000;
char[35] = 80'h0000_0000_0000_0000_0000;
char[36] = 80'h0000_0000_0000_0000_0000;
char[37] = 80'h0000_0000_0000_0000_0000;
char[38] = 80'h07FE_03C0_07E0_0000_0000;
char[39] = 80'h0F3E_0C30_0838_0000_0000;
char[40] = 80'h1C0E_1818_1018_0000_0000;
char[41] = 80'h3C0E_1008_200C_0000_0000;
char[42] = 80'h3806_300C_200C_0000_0000;
char[43] = 80'h7807_300C_300C_0000_0000;
char[44] = 80'h7800_6004_300C_0000_0000;
char[45] = 80'h7000_6006_000C_0000_0000;
char[46] = 80'hF000_6006_0018_0000_0000;
char[47] = 80'hF000_6006_0018_0000_0000;
char[48] = 80'hF000_6006_0030_0000_0000;
char[49] = 80'hF000_6006_0060_0000_0000;
char[50] = 80'hF000_6006_00C0_0000_0000;
char[51] = 80'hF000_6006_0180_0000_0000;
char[52] = 80'hF000_6006_0300_0000_0000;
char[53] = 80'h7802_2006_0200_0000_0000;
char[54] = 80'h7806_300C_0404_0000_0000;
char[55] = 80'h7806_300C_0804_0000_0000;
char[56] = 80'h3C0E_1008_1004_0000_0000;
char[57] = 80'h3C1C_1818_200C_0000_0000;
char[58] = 80'h1FF8_0C30_3FF8_0000_0000;
char[59] = 80'h07F0_03C0_3FF8_0000_0000;
char[60] = 80'h0000_0000_0000_0000_0000;
char[61] = 80'h0000_0000_0000_0000_0000;
char[62] = 80'h0000_0000_0000_0000_0000;
char[63] = 80'h0000_0000_0000_0000_0000;
char[64] = 80'h0000_0000_0000_0000_0000;
end
reg [10:0] hcnt;//行计数
reg [10:0] vcnt;//场计数
//行场同步信号发生
always @(posedge clk_vga or negedge reset)
begin
if(reset)
begin
hcnt <= 'd0;
vcnt <= 'd0;
end
else
begin
if(hcnt == 'd799)//799
begin
hcnt=0;
if(vcnt == 'd524)//524
vcnt=0;
else
vcnt=vcnt+1;
end
else
begin
hcnt=hcnt+1;
end
end
end
//行同步信号输出
assign Hsync = (hcnt <= HSYNCP -1)? HPOLA :~HPOLA;
//场同步信号输出
assign Vsync = (vcnt <= VSYNCP -1)? VPOLA :~VPOLA;
//显示区域的判断
wire h_disp;
assign h_disp = (hcnt > (HSYNCP + HBACKP + LBORDER - 1) && hcnt < (HSYNCP + HBACKP + LBORDER + HDISP - 1))? 1'b1: 1'b0;
wire v_disp;
assign v_disp = (vcnt > (VSYNCP + VBACKP + TBORDER - 1) && vcnt < (VSYNCP + VBACKP + TBORDER + VDISP - 1))? 1'b1: 1'b0;
wire disp;
assign disp = h_disp && v_disp;
always@(posedge clk or negedge reset)
begin
if(reset)
begin
vgaRed <= 4'b0000;
vgaBlue <= 4'b0000;
vgaGreen<= 4'b0000;
end
else if(disp)
begin
if((hcnt >= location_x && hcnt < location_x+80 )&&(vcnt >= location_y && vcnt <location_y+64))
begin
if(char[vcnt-location_y][hcnt-location_x])
begin
vgaRed <= 4'b1111;
vgaBlue <= 4'b1111;
vgaGreen<= 4'b1111;
end
else
begin
vgaRed <= 4'b0000;
vgaBlue <= 4'b0000;
vgaGreen<= 4'b0000;
end
end
else
begin
vgaRed <= 4'b0000;
vgaBlue <= 4'b0000;
vgaGreen<= 4'b0000;
end
end
else
begin
vgaRed <= 4'b0000;
vgaBlue <= 4'b0000;
vgaGreen<= 4'b0000;
end
end
endmodule
我想要达到的结果
FPGA驱动vga显示,生成的是左右镜像的,是整体的镜像,不是单个字符的镜像,不晓得是为什么,pctolcd顺序也是对的,为什么会左右颠倒呢?代码如下