verilog代码case被推断闩锁

Question

这是我在刷HDLbits时遇到的
题目是：
[https://hdlbits.01xz.net/wiki/Fsm_serialdata](Serial receiver and datapath)
类似于实现一个串行通信协议

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset 
    output [7:0] out_byte,
    output done
); 
    localparam START = 0, B1 = 1, B2 = 2, B3 = 3, B4 = 4, B5 = 5, B6 = 6, B7 = 7, B8 = 8, STOP = 9, DONE0 = 10, DONE1 = 11;
    reg [3:0] state, next_state;
    reg [8:1] data = 8'hff;
    
    always@(*) begin
        case(state)
            START: begin
                if(in == 0) begin
                    next_state = B1;
                end
                else 
                    next_state = START;
            end
            B1: begin
                next_state = B2;
                data[1] = in;
            end
            B2: begin
                next_state = B3;
                data[2] = in;
            end
            B3: begin
                next_state = B4;
                data[3] = in;
            end
            B4: begin
                next_state = B5;
                data[4] = in;
            end
            B5: begin
                next_state = B6;
                data[5] = in;
            end
            B6: begin
                next_state = B7;
                data[6] = in;
            end
            B7: begin
                next_state = B8;
                data[7] = in;
            end
            B8: begin
                next_state = STOP;
                data[8] = in;
            end
            STOP: begin
                if(in == 0) next_state = DONE1;
                else next_state = DONE0;
            end
            DONE0: begin
                if(in == 1)
                    next_state = START;
                else 
                    next_state = B1;
            end
            DONE1: begin
                if(in == 0) 
                    next_state = DONE1;
                else 
                    next_state = START;
            end
            default: begin
                next_state = START;
            end
            
        endcase
    end
    
    always@(posedge clk) begin
        if(reset) 
            state <= START;
        else 
            state <= next_state;
    end
    
    assign done = (state == DONE0) ? 1 : 0;
    assign out_byte[7:0] = done ? data[8:1] : {8{1'bz}};
    
    
endmodule

我在进行仿真时总是警告case推断出闩锁，搞的我一头雾水。
这是咋回事呢？

Answer 1

在代码中，已经存在一个闩锁状态，也就是当state等于START或B1时，如果in的值为0，next_state将被设置为B1或START，这导致下一个时钟周期state仍然为START或B1，如此反复，就产生了所谓的闩锁状态。

为了解决这个问题，可以修改代码，将in的值与某个固定的信号进行对比，例如reset信号。这样可以保证在任何情况下，state都不会被无限循环地重复执行。

具体修改如下：

always@(posedge clk) begin
    if(reset) 
        state <= START;
    else if (reset || in == 0) 
        state <= START;
    else 
        state <= next_state;
end

此外，代码中的某些状态在实际应用中可能并不会使用到，例如B1状态。在实际应用中，可以考虑删除这些状态，以简化代码和提高效率。