library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity weideng is
port(clk,tright,tleft,jingji:in std_logic;
rightdeng:out std_logic_vector(2 downto 0);
leftdeng:out std_logic_vector(2 downto 0));
end weideng;
architecture qiche of weideng is
signal rightd:std_logic_vector(1 downto 0);
signal leftd:std_logic_vector(1 downto 0);
signal jingjid:std_logic_vector(1 downto 0);
begin
control:process(clk,tleft,tright)
begin
if clk'event and clk='1'then
if rightd="01"then rightd<="11";
else rightd<=(rightd-1);
end if;
if leftd<="01" then leftd<="11";
else leftd<=(leftd-1);
end if;
if(jingjid="01") then
jingjid<="11";
else
jingjid<=(jingjid-1);
end if;
end if;
end process control;
proout:process(clk,tright,tleft,rightd,leftd,jingjid)
begin
if clk'event and clk='1'then
if tright='1'then leftdeng<="000";
case rightd is
when"01"=>rightdeng<="001";
when"10"=>rightdeng<="010";
when"11"=>rightdeng<="100";
when others=>rightdeng<="000";
end case;
elsif tright='0' then rightdeng<="000";
case leftd is
when"01"=>leftdeng<="100";
when"10"=>leftdeng<="010";
when"11"=>leftdeng<="001";
when others=>leftdeng<="000";
end case;
elsif tleft='0'then leftdeng<="000";
end if;
end if;
if tleft='1'and tright='1'then
leftdeng<="111";
rightdeng<="111";
elsif tleft='0'and tright='0'then
leftdeng<="000";
rightdeng<="000";
end if;
if(jingji='1')then
case jingjid is
when"01"=>leftdeng<="000";
rightdeng<="000";
when"10"=> leftdeng<="111";
rightdeng<="111";
when"11"=> leftdeng<="000";
rightdeng<="000";
when others=>leftdeng<="111";
rightdeng<="111";
end case;
end if;
end process proout;
end qiche;
