Verilog改错 testbench

Question

testbench有几个问题比较雷同 但不知道为什么 都显示最后括号里的内容错了

`timescale 1ns/1ps
module count_test;
reg clk;
wire a,b,c,d,e,f,g;
wire[1:0] outa;
wire qout;
wire LAMP;
reg reset,load,cin,data,ud;
count count (clk,a,b,c,d,e,f,g,qout,reset,load,cin,data,ud);
initial begin
clk=1'b0;
reset=1'b1;
cin=1'b0;
data=1'b0;
ud=1'b1;
load=1'b1;
#10
reset=1'b0;
load=1'b0;

always
#10
clk=~clk;
count(
  .clk(clk),
  .load(load),
  .reset(reset),
  .data(data),
  .cin(cin),
  .ud(ud),
);
end
endmodule

** Error: C:/modeltech_10.1a/examples/test.v(21): near "always": syntax error, unexpected always
** Error: C:/modeltech_10.1a/examples/test.v(25): Named argument not allowed in verilog.
** Error: C:/modeltech_10.1a/examples/test.v(26): Named argument not allowed in verilog.
** Error: C:/modeltech_10.1a/examples/test.v(27): Named argument not allowed in verilog.
** Error: C:/modeltech_10.1a/examples/test.v(28): Named argument not allowed in verilog.
** Error: C:/modeltech_10.1a/examples/test.v(29): Named argument not allowed in verilog.
** Error: C:/modeltech_10.1a/examples/test.v(30): Named argument not allowed in verilog.
** Error: C:/modeltech_10.1a/examples/test.v(31): Empty argument not allowed in verilog.

Answer 1

always好像不能放在initial语句中，always下面语句应该是块语句吧