ESP8266-SDK 串口中断 接收数据的FIFO有一个接收超时时间,请问接收超时时间在哪里设置? 20C

可以知道当串口中断被触发后,会将数据存入FIFO,FIFO有一个接收超时中断位
UART_RXFIFO_TOUT_INT_ST,那么FIFO的接收超时时间在哪里可以设置?

1个回答

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/* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "can.h" #include "usart.h" #include "gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ void CAN_SetTxMsg(void) { hcan.pTxMsg->ExtId=0x1314; //使用的扩展ID hcan.pTxMsg->IDE=CAN_ID_EXT; //扩展模式 hcan.pTxMsg->RTR=CAN_RTR_DATA; //发送的是数据 hcan.pTxMsg->DLC=8; //数据长度为2字节 hcan.pTxMsg->data[0]=0x01; hcan.pTxMsg->data[1]=0x02; hcan.pTxMsg->data[2]=0x03; hcan.pTxMsg->data[3]=0x04; hcan.pTxMsg->data[4]=0x05; hcan.pTxMsg->data[5]=0x06; hcan.pTxMsg->data[6]=0x07; hcan.pTxMsg->data[7]=0x08; } /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN PTD */ /* USER CODE END PTD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /** * @brief The application entry point. * @retval int */ int main(void) { /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_CAN_Init(); MX_USART1_UART_Init(); /* USER CODE BEGIN 2 */ CAN_SetTxMsg(); HAL_CAN_AddTxMessage(&hcan,hcan.pTxMsg,hcan.pTxMsg->data,(uint32_t*)CAN_TX_MAILBOX0); HAL_CAN_ActivateNotification(&hcan,CAN_IT_RX_FIFO0_MSG_PENDING); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ } /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { Error_Handler(); } /** Enables the Clock Security System */ HAL_RCC_EnableCSS(); } /* USER CODE BEGIN 4 */ void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { HAL_CAN_AddTxMessage(hcan,hcan->pTxMsg,hcan->pTxMsg->data,(uint32_t*)CAN_TX_MAILBOX0); HAL_CAN_ActivateNotification(hcan,CAN_IT_RX_FIFO0_MSG_PENDING); } /* USER CODE END 4 */ /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** * @brief Reports the name of the source file and the source line number * where the assert_param error has occurred. * @param file: pointer to the source file name * @param line: assert_param error line source number * @retval None */ void assert_failed(uint8_t *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 这是我的主程序,debug总是在CAN_SetMsg()那里进入了hardfault.下面是定义的一些初始化结构体。 /** ****************************************************************************** * @file stm32f1xx_hal_can.h * @author MCD Application Team * @brief Header file of CAN HAL module. ****************************************************************************** * @attention * * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F1xx_HAL_CAN_H #define STM32F1xx_HAL_CAN_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ #if defined (CAN1) /** @addtogroup CAN * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ */ /** * @brief HAL State structures definition */ typedef enum { HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ } HAL_CAN_StateTypeDef; /** * @brief CAN init structure definition */ typedef struct { uint32_t Prescaler; /*!< Specifies the length of a time quantum. This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ uint32_t Mode; /*!< Specifies the CAN operating mode. This parameter can be a value of @ref CAN_operating_mode */ uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of @ref CAN_synchronisation_jump_width */ uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. This parameter can be set to ENABLE or DISABLE. */ FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. This parameter can be set to ENABLE or DISABLE. */ FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. This parameter can be set to ENABLE or DISABLE. */ FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. This parameter can be set to ENABLE or DISABLE. */ FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. This parameter can be set to ENABLE or DISABLE. */ FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. This parameter can be set to ENABLE or DISABLE. */ } CAN_InitTypeDef; /** * @brief CAN filter configuration structure definition */ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. For single CAN instance(14 dedicated filter banks), this parameter must be a number between Min_Data = 0 and Max_Data = 13. For dual CAN instances(28 filter banks shared), this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ uint32_t FilterScale; /*!< Specifies the filter scale. This parameter can be a value of @ref CAN_filter_scale */ uint32_t FilterActivation; /*!< Enable or disable the filter. This parameter can be a value of @ref CAN_filter_activation */ uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. For single CAN instances, this parameter is meaningless. For dual CAN instances, all filter banks with lower index are assigned to master CAN instance, whereas all filter banks with greater index are assigned to slave CAN instance. This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ } CAN_FilterTypeDef; /** * @brief CAN Tx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ uint8_t data[8]; FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. @note: Time Triggered Communication Mode must be enabled. @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. This parameter can be set to ENABLE or DISABLE. */ } CAN_TxHeaderTypeDef; /** * @brief CAN Rx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ uint8_t Data[8]; uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. @note: Time Triggered Communication Mode must be enabled. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ } CAN_RxHeaderTypeDef; /** * @brief CAN handle Structure definition */ typedef struct __CAN_HandleTypeDef { CAN_TypeDef *Instance; /*!< Register base address */ CAN_InitTypeDef Init; /*!< CAN required parameters */ CAN_TxHeaderTypeDef* pTxMsg; CAN_RxHeaderTypeDef* pRxMsg; HAL_LockTypeDef Lock; __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ __IO uint32_t ErrorCode; /*!< CAN Error code. This parameter can be a value of @ref CAN_Error_Code */ } CAN_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup CAN_Exported_Constants CAN Exported Constants * @{ */ /** @defgroup CAN_Error_Code CAN Error Code * @{ */ #define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ #define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ #define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ #define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ #define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ #define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ #define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ #define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ #define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ #define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ #define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ #define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ #define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ #define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ #define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ #define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ #define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ #define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ #define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ #define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ #define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ #define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ #define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ #define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ /** * @} */ /** @defgroup CAN_InitStatus CAN InitStatus * @{ */ #define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ #define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ #define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ /** * @} */ /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ #define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ #define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ #define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ /** * @} */ /** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ #define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ #define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ /** * @} */ /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ #define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ #define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ /** * @} */ /** @defgroup CAN_filter_activation CAN Filter Activation * @{ */ #define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ #define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ /** * @} */ /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ #define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ /** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ #define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ #define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ /** * @} */ /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ #define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ #define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ /** * @} */ /** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number * @{ */ #define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ #define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ /** * @} */ /** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes * @{ */ #define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ #define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ #define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ /** * @} */ /** @defgroup CAN_flags CAN Flags * @{ */ /* Transmit Flags */ #define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ #define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ #define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ #define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ #define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ #define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ #define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ #define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ #define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ #define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ #define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ #define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ #define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ #define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ #define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ #define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ #define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ #define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ /* Receive Flags */ #define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ #define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ #define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ #define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ /* Operating Mode Flags */ #define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ #define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ #define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ #define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ #define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ /* Error Flags */ #define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ #define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ #define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} */ /** @defgroup CAN_Interrupts CAN Interrupts * @{ */ /* Transmit Interrupt */ #define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ #define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ #define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ #define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ #define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ #define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ #define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ /* Operating Mode Interrupts */ #define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ #define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ /* Error Interrupts */ #define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ #define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ #define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ #define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ #define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ /** @brief Reset CAN handle state * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** * @brief Enable the specified CAN interrupts. * @param __HANDLE__ CAN handle. * @param __INTERRUPT__ CAN Interrupt sources to enable. * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** * @brief Disable the specified CAN interrupts. * @param __HANDLE__ CAN handle. * @param __INTERRUPT__ CAN Interrupt sources to disable. * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) /** @brief Check if the specified CAN interrupt source is enabled or disabled. * @param __HANDLE__ specifies the CAN Handle. * @param __INTERRUPT__ specifies the CAN interrupt source to check. * This parameter can be a value of @arg CAN_Interrupts * @retval The state of __IT__ (TRUE or FALSE). */ #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) /** @brief Check whether the specified CAN flag is set or not. * @param __HANDLE__ specifies the CAN Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of @arg CAN_flags * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Clear the specified CAN pending flag. * @param __HANDLE__ specifies the CAN Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup CAN_Exported_Functions CAN Exported Functions * @{ */ /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @{ */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); /** * @} */ /** @addtogroup CAN_Exported_Functions_Group2 Configuration functions * @brief Configuration functions * @{ */ /* Configuration functions ****************************************************/ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); /** * @} */ /** @addtogroup CAN_Exported_Functions_Group3 Control functions * @brief Control functions * @{ */ /* Control functions **********************************************************/ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); /** * @} */ /** @addtogroup CAN_Exported_Functions_Group4 Interrupts management * @brief Interrupts management * @{ */ /* Interrupts management ******************************************************/ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); /** * @} */ /** @addtogroup CAN_Exported_Functions_Group5 Callback functions * @brief Callback functions * @{ */ /* Callbacks functions ********************************************************/ void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); /** * @} */ /** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions * @brief CAN Peripheral State functions * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /** @defgroup CAN_Private_Types CAN Private Types * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /** @defgroup CAN_Private_Variables CAN Private Variables * @{ */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ #define CAN_FLAG_MASK (0x000000FFU) /** * @} */ /* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) #define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) #define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) #define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) #if defined(CAN2) #define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) #endif #define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) #define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ ((ACTIVATION) == CAN_FILTER_ENABLE)) #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) #define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) #define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) #define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) #define IS_CAN_DLC(DLC) ((DLC) <= 8U) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) #define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) #define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) /** * @} */ /* End of private macros -----------------------------------------------------*/ /** * @} */ #endif /* CAN1 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F1xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 求大佬指点哪里错了。。
求代码,求代码,在Ubuntu下编制一个程序,模拟实现一个简单的进程管理子系统,它由进程建立模块、进程撤消模块、进程控制表组成,并包括进程切换和调度模块?
在Ubuntu下编制一个程序,模拟实现一个简单的进程管理子系统,它由进程建立模块、进程撤消模块、进程控制表组成,并包括进程切换和调度模块。 【设计要求1】 该子系统接收新进程建立请求的方式是循环显示“请输入新命令行”,然后根据用户键入内容启动相应进程,其后不等待子进程结束,马上显示下一个“请输入新命令行”如此循环往复。 当建立进程时,相应读写进程控制表,然后借助底层环境OS中像fork和exec这样的函数将新进程投入运行(这与底层环境的实际OS不同,实际OS将新进程投入运行时要布置现场,最后时程序技术器寄存器)。进程撤消时,利用底层OS的wait( )从子进程回到本子系统,相应修改PCB。 比较该子系统与实际系统中的相应功能的异同与差距,尤其在现场保存与恢复方面的比较。 【设计要求2】 在上题的基础上,进一步模拟实现进程切换。希望能实现时间片满或接到sleep调用(或信号时)进行进程切换(选择其一即可)。 若要实现时间片,假设时间片为1秒钟,设定底层环境OS每个1秒向该系统发一个信号,本子系统将本子系统的进程切换和调度模块设定为该信号的处理程序。或者每当接到子进程发出的的sleep调用(或信号)时进行进程切换,这里子进程发出的sleep调用(或信号)代表实际系统中可能发生的sleep( )调用、等待某一时间发生等情况,进程调度采用简单的FIFO算法。
Generational Replacement
Description Erik G. Hallnor and Steven K. Reinhardt from the University of Michigan suggested a fully associative software-managed cache design in ISCA (International Symposium on Computer Architecture) 2000. They have two primary contributions: a practical design for a fully associative memory structure, the indirect index cache (IIC), and a novel replacement algorithm, generational replacement, that is specifically designed to work with the IIC. They analyze the behavior of an IIC with generational replacement as a drop-in, transparent substitute for a conventional secondary cache, and achieve miss rate reductions from 8% to 85% relative to a 4-way associative LRU organization, matching or beating a (practically infeasible) fully associative true LRU cache. Incorporating these miss rates into a rudimentary timing model indicates that the IIC/generational replacement cache could be competitive with a conventional cache at today's DRAM latencies, and will outperform a conventional cache as these CPU-relative latencies grow. The indirect index cache (IIC) provides a practical implementation of a fully associative data store using indirection, mapping physical addresses to data array indices in a manner similar to page-table based virtual-to-physical address translation. Unlike virtual address translation, the IIC is transparent to the operating system. Also unlike virtual memory, the IIC initiates miss handling in hardware, keeping software off the critical path of main-memory accesses. The generational replacement algorithm, as we focus here, is described in the paper as following: "Although the IIC design is independent of the replacement algorithm used to manage it, its utility depends on the existence of a practical algorithm that provides competitive performance without unreasonable overhead. This section presents a novel algorithm we have developed, called generational replacement ...... As described above, the motivation for generational replacement is to cope with the reduced information provided by secondary-cache reference bits. Specifically, under generational replacement a block that happens not to have its reference bit set during a particular interval is not considered a candidate for replacement if it has been repeatedly referenced in the recent past. Unfortunately, maintaining even approximate reference frequency counters based on reference bits is time consuming. Instead, we group blocks into a small number of prioritized pools. We promote blocks that are referenced regularly into higher-priority pools, and demote unreferenced blocks into lower-priority pools. On a miss, the block to be replaced is chosen from the lowest-priority nonempty pool. We call the algorithm "generational replacement" based on the notion that frequently-accessed blocks are promoted into senior generations, somewhat like long-lived objects are promoted in generational garbage collection." The figure illustrates the algorithm. In the figure, there are 4 prioritized pools. Each pool is a variable length FIFO queue of blocks. On a hit, only the block's reference bit is set. On each miss, after fetching the new block, the algorithm checks the head of each pool FIFO sequentially from the highest-priority one to the lowest-priority one. If the head block's reference bit is set, it is promoted to the next higher-priority pool - the block in the highest priority pool will be promoted to the same pool; if the reference bit is not set, the block is demoted to the next lower-priority pool - the block in the lowest priority pool will be replaced out of cache. In either case, the reference bit is cleared, and the block is placed at the tail of the new pool's FIFO. The new block fetched into cache is placed at the tail of the highest priority pool with its reference bit unset. You are requested to read a series of IIC performance, implement the generational replacement algorithm and describe the final state of the storage situation. Extra introduction:Cache was the name chosen to represent the level of memory hierarchy between the CPU and main memory in the first commercial machine to have this extra level. It is used to diminish the speed gap between the fast CPU and relevant slow DRAM memory under the principle of locality. Cache is organized with address indexed blocks directly or indirectly mapped into the blocks in main memory. When CPU wants to visit the block in the main memory, it first looks for the content wanted in the cache. A hit means the block CPU needs is just in the cache and it may just fetch the data stored in cache without visiting the slow memory. Otherwise, a miss happens when the block CPU needs doesn't exist in cache, so CPU will search the block in main memory and exchange it into cache for further visit and discard the block not preferred if there is not enough room in cache. A fully associative cache means the block in memory may be associated with any entry in the cache, not mapped by address. This is an extreme scheme. Input There are several test cases in the input. Each starts with the integer N (1<= N <= 10) representing the number of prioritized pools. Then the following lines describe the IIC performance - blocks sequences requested by CPU, in such format: 0x12345678 2 The 8-bit hex-decimal number represents the address of the block CPU requested and followed an integer representing the number of times this block is sequentially requested. For example, the block request sequence is: 0x11111111 0x11111111 0x11111111 0x22222222 0x22222222 0x22222222 0x22222222 0x33333333... will be given in such format: 0x11111111 3 0x22222222 4 0x33333333 1 The block sequence will be ended with # and the test case will be ended with N = 0. Output For each test case, you are requested to print address of each block from head to tail in every pool queue. Pools are sequentially numbered just as the figure shows. From pool 0 to pool n-1, each pool a line, the format is like this: PoolNumber: BlockAdd1 BlockAdd2 ... BlockAddm You may assume that at the beginning of each test case, the pools are all empty. You should print a blank line between test cases. Sample Input 4 0x11111111 1 0x22222222 1 0x33333333 1 0x44444444 1 0x55555555 1 # 0 Sample Output 0: 0x22222222 1: 0x33333333 2: 0x44444444 3: 0x55555555
友善之臂mini2440 运行uart裸板程序失败
用的板子是友善之臂mini2440,自己学习韦东山的一期视频,在写uart裸板程序时发现怎么都无法实现功能 s3c2440.h ``` /* GPIO寄存器 */ #define GPBCON (*(volatile unsigned int*)0x56000010) #define GPGCON (*(volatile unsigned int*)0x56000060) #define GPHCON (*(volatile unsigned int*)0x56000070) #define GPBDAT (*(volatile unsigned int*)0x56000014) #define GPGDAT (*(volatile unsigned int*)0x56000064) #define GPHUP (*(volatile unsigned int*)0x56000078) /* UART寄存器 */ #define UCON0 (*(volatile unsigned int*)0x50000004) #define UBRDIV0 (*(volatile unsigned int*)0x50000004) #define ULCON0 (*(volatile unsigned int*)0x50000028) #define UTRSTAT0 (*(volatile unsigned int*)0x50000010) #define UTXH0 (*(volatile unsigned char*)0x50000020) #define URXH0 (*(volatile unsigned char*)0x50000024) #define UFCON0 (*(volatile unsigned int*)0x50000008) #define UMCON0 (*(volatile unsigned int*)0x5000000C) #define UCON1 (*(volatile unsigned int*)0x50004004) #define UBRDIV1 (*(volatile unsigned int*)0x50004028) #define ULCON1 (*(volatile unsigned int*)0x50004000) #define UTRSTAT1 (*(volatile unsigned int*)0x50004010) #define UTXH1 (*(volatile unsigned char*)0x50004020) #define URXH1 (*(volatile unsigned char*)0x50004024) #define UFCON1 (*(volatile unsigned int*)0x50004008) #define UMCON1 (*(volatile unsigned int*)0x5000400C) ``` uart.h ``` #ifndef _UART_H #define _UART_H void uart0_init(); int putchar(int c); int getchar(void); int puts(const char *s); #endif ``` uart.c ``` #include "s3c2440.h" /* 设置引脚用于串口 */ void uart0_init() { GPHCON &= ~((3<<8)|(3<<10)); //清空GPH2,GPH3 GPHCON |= ((2<<8)|(2<<10)); //GPH4,GPH5用于TXD1,RXD1 GPHUP &= ~((1<<4)|(1<<5)); //使能内部上拉 UFCON0 = 0x00; //不使用FIFO UMCON0 = 0x00; //不使用流控 ULCON0 = 0x00000003; //设置数据格式8n1:8位数据位,无校验位,1停止位 UCON0 = 0x00000005; //PCLK,中断/查询模式 UBRDIV0 = 26; //设置波特率 115200 } int putchar(int c) { while(!(UTRSTAT0) & (1<<2)) UTXH0 = (unsigned char)c; } int getchar(void) { while(!(UTRSTAT0) & (1<<0)) return URXH0; } int puts(const char *s) { while(*s) { putchar(*s); s++; } } ``` main.c ``` #include "s3c2440.h" #include "uart.h" int main(void) { unsigned char c; uart0_init(); puts("hello,world!\n"); while(1) { c = getchar(); putchar(c); } return 0; } ``` start.S ``` .text .global _start _start: /*设置内存:sp 栈*/ ldr sp,=4096 /*nand启动*/ /* 关闭看门狗 */ ldr r0, =0x53000000 ldr r1, =0 str r1, [r0] /* 设置CPU工作于异步模式 */ mrc p15,0,r0,c1,c0,0 orr r0,r0,#0xc0000000 //R1_nF:OR:R1_iA mcr p15,0,r0,c1,c0,0 /* 设置MPLL,FCLK */ /* CLKDIVN(0x4c000014) = 0x5 */ ldr r0, =0x4c000014 ldr r1, =0x5 /* HCLK = FCLK/4 = 100 MHz , PCLK = HCLK/2 = 50MHz */ str r1, [r0] /* 设置MPLLCON(0x4c000004) = (92<<12)|(1<<4)|(1<<0) FCLK = 400 MHz*/ ldr r0, =0x4c000004 ldr r1, =(92<<12)|(1<<4)|(1<<0) str r1,[r0] /*调用main*/ bl main halt: b halt ``` Makefile ``` all: arm-linux-gcc -c -o uart.o uart.c arm-linux-gcc -c -o main.o main.c arm-linux-gcc -c -o start.o start.S arm-linux-ld -Ttext 0 start.o uart.o main.o -o uart.elf arm-linux-objcopy -O binary -S uart.elf uart.bin arm-linux-objdump -D uart.elf > uart.dis clean: rm *.bin *.o *.elf *.dis ``` 程序写完后扔到虚拟机里编译生成.bin文件,之后用友善之臂自己编写的下载工具进行烧写 ![图片说明](https://img-ask.csdn.net/upload/202001/07/1578379644_335442.png) 之后选择nand启动,连接串口,并没有看到返回字符串hello,world! 特来请教
linux MPU9250怎样开启DMP,FIFO读取数据
已经移植了好些天了,没进展,先在stm32f4上移植了一下,DMP和MPL初始化都没报什么错,但是调用mpu_dmp_get_data读取fifo处理获得的picth,roll,yaw的值没变化,而直接读取temp,accl,gyro的寄存器数据正确的。不知道DMP哪了出问题了,各位大神有在linux下移植了吗,有源码?怎么操作?
终于明白阿里百度这样的大公司,为什么面试经常拿ThreadLocal考验求职者了
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