在用Quartus II综合SoC,工程里加入了PLL Intel FPGA IP后,就出现了如下错误:
Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis
如果注释掉PLL部分就没错误了。
是需要修改处理器的Cache吗?
使用的版本是(Quartus Prime 18.1) Standard Edition,恳请给出具体解答!!