请分析如下所示的Verilog程序功能,并编写仿真测试程序
module reg8(input clk, input clrn, input wen, input [7:0] d, output [7:0] q);
reg [7:0] p;
always @(posedge clk or negedge clrn)
if(!clrn)
p<= 0;
else if (!wen)
p <= d;
assign q = p;
endmodule