beijipangxiongmao
beijipangxiongmao
2017-11-27 15:58

verilog4位加法器仿真

  • verilog

v程序为module add_4(X,Y,sum,C);
input[3:0] X,Y;
output[3:0] sum;
output C;
assign {C, Sum }=X+Y;
endmodule
要使用modelsim仿真,生成的vt文件应该怎么修改?
`timescale 1 ps/ 1 ps
module add_4_vlg_tst();
// constants

// general purpose registers

// test vector input registers
reg clk;
reg [3:0] X;
reg [3:0] Y;
// wires

wire C;
wire [3:0] sum;

// assign statements (if any)

add_4 i1 (
// port map - connection between master ports and signals/registers

.C(C),
.X(X),
.Y(Y),
.sum(sum)
);
initial

begin

// code that executes only once

// insert code here --> begin

// --> end

$display("Running testbench");

end

always

// optional sensitivity list

// @(event1 or event2 or .... eventn)

begin

// code executes for every event on sensitivity list

// insert code here --> begin

// --> end

end

endmodule

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