`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/06/04 10:39:05
// Design Name:
// Module Name: gcd_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module gcd_1(
input clk, input clr,
input [3:0] xin,input [3:0] yin,
output [3:0] gcd
);
wire [3:0] gcd_2;
wire eqflg; wire ltflg;
wire xmsel; wire ymsel;
wire xld; wire yld; wire gld;
gcd_1_Controller ControllerUnit(
.clk(clk),
.clr(clr),
.eqflg(eqflg),
.ltflg(ltflg),
.xmsel(xmsel),
.ymsel(ymsel),
.xld(xld),
.yld(yld),
.gld(gld)
);
gcd_1_DataPath DataPathUnit(
.clk(clk),
.clr(clr),
.xld(xld),
.yld(yld),
.gld(gld),
.xmsel(xmsel),
.ymsel(ymsel),
.xin(xin),
.yin(yin),
.eqflg(eqflg),
.ltflg(ltflg),
.gcd(gcd_2)
);
assign gcd = gcd_2;
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/06/04 10:39:05
// Design Name:
// Module Name: gcd_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module gcd_1_Controller(
input clk, input clr,
input go,
input eqflg,input ltflg,
output reg xmsel, output reg ymsel,
output reg xld, output reg yld, output reg gld
);
reg [2:0] state,nstate;
parameter start = 3'b000, input1 = 3'b001, test1 = 3'b010,
test2 = 3'b011 ,update1 = 3'b100,update2 = 3'b101, done = 3'b110;
//state register
always @(posedge clk) begin
if (clr) begin
// reset
state <= start;
end
else begin
state <= nstate;
end
end
//next state logic
always@(*) begin
case(state)
start: begin
if (go == 1)
nstate = input1;
else
nstate = start; end
input1:
nstate = test1;
test1: begin
if (eqflg == 1) begin
nstate = done;
end
else begin
nstate = test2;
end end
test2:begin
if (ltflg == 1) begin
nstate = update1;
end
else begin
nstate = update2;
end
end
update1:begin
nstate = test1;
xld = 0;
yld = 1; gld = 0; end
update2: begin
nstate = test1;
xld = 1; yld = 0;gld = 0; end
done: begin
xld = 0; yld = 0 ;gld = 1;
nstate = done; end
default:
nstate = start;
endcase
end
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: SYSU.MST
// Engineer: He Yongjun
//
// Create Date: 2021/06/04 10:39:05
// Design Name: implement of gcd
// Module Name: gcd_1
// Project Name: implement of gcd
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module gcd_1_DataPath(
input clk, input clr,
input xmsel, input ymsel,
input xld ,input yld ,input gld,
input [3:0] xin, input [3:0] yin,
output [3:0] gcd,
output reg eqflg, output reg ltflg);
wire [3:0] xmy, ymxt;
reg [3:0] x, y, x1,y1, gcd_out;//最难区分的就是wire和reg！！
assign xmy = x - y;//减法器
assign ymx = y - x;//减法器
always @(*) begin//判断机
if (x == y) begin
eqflg = 1;
ltflg = 0;
end
else if (x < y) begin
eqflg = 0;
ltflg = 1;
end
else begin
eqflg = 0;
ltflg = 0;
end
end
always @(*) begin //mux_x
if (xmsel == 1)begin
x1 = xmy;
end
else begin
x1 = 0;
end
end
always @(*) begin //mux_y
if (ymsel == 1)begin
y1 = ymx;
end
else begin
y1 = 0;
end
end
always @(posedge clk) begin
if (clr) begin
x <= 0;// reset
end
else if(xld == 1) begin
x <= x1;
end
end
always @(posedge clk) begin
if (clr) begin
y <= 0;// reset
end
else if(yld == 1) begin
y <= y1;
end
end
always @(posedge clk) begin
if (clr) begin
gcd_out <= 0;// reset
end
else if(gld == 1) begin
gcd_out <= y1;
end
end
assign gcd = gcd_out;
endmodule
