VHDL实现移位寄存器结果不对

Question

还是老问题（汗），虽然会显示结果但结果不对头。任务是实现一个PISO移位寄存器：

虽然这次成功了但是结果不对头啊。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity D_FF is
  port (
    D : in std_logic;
    CLK : in std_logic;
    Q : out std_logic
  );
end entity D_FF;
 
architecture D_FF_arch of D_FF is
begin
  process (CLK)
  begin
    if rising_edge(CLK) then
      Q <= D;
    end if;
  end process;
end architecture D_FF_arch;
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity PISO is
    port (
        D0, D1, D2, D3 : in std_logic;
        SHIFT_LOAD : in std_logic;
        CLK : in std_logic;
        Q3 : out std_logic
    );
end entity PISO;
 
architecture behavioral of PISO is
    signal D_out : STD_LOGIC_VECTOR(3 downto 0);
    signal Q2 : STD_LOGIC;
begin
    DFF_3: entity work.D_FF port map (D3, CLK, D_out(3));
    DFF_2: entity work.D_FF port map (D2, CLK, D_out(2));
    DFF_1: entity work.D_FF port map (D1, CLK, D_out(1));
    DFF_0: entity work.D_FF port map (D0, CLK, D_out(0));
 
    Q2 <= D_out(2);
 
    process (CLK)
    begin
        if rising_edge(CLK) then
            if SHIFT_LOAD = '0' then
                D_out <= D3 & D2 & D1 & D0;
            else
                D_out <= '0' & D_out(3 downto 1);
            end if;
        end if;
    end process;
 
    Q3 <= D_out(3);
end behavioral;

测试台文件

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity lab1_test is
end lab1_test;
 
architecture tb of lab1_test is
    signal D3, D2, D1, D0, SHIFT_LOAD, CLK : STD_LOGIC := '0';
    signal Q3 : STD_LOGIC;
    component PISO is
        Port ( D0, D1, D2, D3, SHIFT_LOAD, CLK : in STD_LOGIC; 
               Q3 : out STD_LOGIC);
    end component;
begin
    dut: PISO
    port map (D0, D1, D2, D3, SHIFT_LOAD, CLK, Q3); 
 
    CLK_process: process
    begin
    wait for 2.5 ns; 
    CLK <= not CLK;
    end process;
 
    stimulus: process
    begin
        wait for 10 ns;
        D3 <= '1'; D2 <= '0'; D1 <= '1'; D0 <= '0'; SHIFT_LOAD <= '0'; -- Input data
        wait for 10 ns;
        SHIFT_LOAD <= '1'; -- Shift data
        wait for 10 ns;
        D3 <= '0'; D2 <= '0'; D1 <= '1'; D0 <= '1'; SHIFT_LOAD <= '0'; -- Input new data
        wait for 10 ns;
        SHIFT_LOAD <= '1'; -- Shift data again
        wait;
    end process;
end Behavioral;

麻了，还是有问题，麻烦大家了。

Answer 1

让阿豪来帮你解答，本回答参考chatgpt3.5编写提供，如果还有疑问可以评论或留言

问题描述： 实现一个 PISO 移位寄存器，代码已经书写，结果显示有问题。 解决方案： 代码中存在以下问题： 1.在 PISO 的结构体中，D_out 信号应该定义为 STD_LOGIC_VECTOR(3 downto 0)，即一个 4 位的向量，而不是信号定义为一个 std_logic 类型。

1. CLK_process 进程中的时间延迟应该是 5ns，因为 CLK 的周期为 10ns，所以需要等待一半的时间。 修改后的代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_FF is
  port (
    D : in std_logic;
    CLK : in std_logic;
    Q : out std_logic
  );
end entity D_FF;
architecture D_FF_arch of D_FF is
begin
  process (CLK)
  begin
    if rising_edge(CLK) then
      Q <= D;
    end if;
  end process;
end architecture D_FF_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PISO is
  port (
    D0, D1, D2, D3 : in std_logic;
    SHIFT_LOAD : in std_logic;
    CLK : in std_logic;
    Q3 : out std_logic
  );
end entity PISO;
architecture behavioral of PISO is
  signal D_out : std_logic_vector(3 downto 0);
  signal Q2 : std_logic;
begin
  -- 将 D_out 信号定义为一个 4 位向量
  DFF_3: entity work.D_FF port map (D3, CLK, D_out(3));
  DFF_2: entity work.D_FF port map (D2, CLK, D_out(2));
  DFF_1: entity work.D_FF port map (D1, CLK, D_out(1));
  DFF_0: entity work.D_FF port map (D0, CLK, D_out(0));
  Q2 <= D_out(2);
  process (CLK)
  begin
    if rising_edge(CLK) then
      if SHIFT_LOAD = '0' then
        D_out <= D3 & D2 & D1 & D0;
      else
        D_out <= '0' & D_out(3 downto 1);
      end if;
    end if;
  end process;
  Q3 <= D_out(3);
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lab1_test is
end lab1_test;
architecture tb of lab1_test is
  signal D3, D2, D1, D0, SHIFT_LOAD, CLK : STD_LOGIC := '0';
  signal Q3 : STD_LOGIC;
  component PISO is
    Port (
      D0, D1, D2, D3, SHIFT_LOAD, CLK : in STD_LOGIC;
      Q3 : out STD_LOGIC
    );
  end component;
begin
  dut: PISO port map (D0, D1, D2, D3, SHIFT_LOAD, CLK, Q3);
  -- 时间延迟应该为 5ns
  CLK_process: process
  begin
    wait for 5 ns;
    CLK <= not CLK;
    wait for 5 ns;
    CLK <= not CLK;
  end process;
  stimulus: process
  begin
    wait for 10 ns;
    D3 <= '1'; D2 <= '0'; D1 <= '1'; D0 <= '0'; SHIFT_LOAD <= '0'; -- Input data
    wait for 10 ns;
    SHIFT_LOAD <= '1'; -- Shift data
    wait for 10 ns;
    D3 <= '0'; D2 <= '0'; D1 <= '1'; D0 <= '1'; SHIFT_LOAD <= '0'; -- Input new data
    wait for 10 ns;
    SHIFT_LOAD <= '1'; -- Shift data again
    wait;
  end process;
end Behavioral;