8255VHDL语言波形问题

Question

下面的这个程序在ModelSim SE运行怎么没波形
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY ppi IS
PORT(reset,rd,wr,cs,a0,a1:IN std_logic;
pa:INOUT std_logic_vector(7 downto 0);
pb:INOUT std_logic_vector(7 downto 0);
pcl:INOUT std_logic_vector(3 downto 0);
pch:INOUT std_logic_vector(3 downto 0);
d:INOUT std_logic_vector(7 downto 0));

END ppi;

ARCHITECTURE Behavioral OF ppi IS
SIGNAL internal_bus:std_logic_vector(7 downto 0);
SIGNAL st,ad,flag:std_logic_vector(1 downto 0);
SIGNAL ctrreg:std_logic_vector(7 downto 0);
SIGNAL pa_latch,pb_latch,pc_latch:std_logic_vector(7 downto 0);
BEGIN

PROCESS(rd,cs)
BEGIN
st<=ctrreg(3)&ctrreg(0);
IF(cs='0'AND rd='0')THEN
IF(a0='0' and a1='0' and ctrreg(4)='1')THEN
internal_bus<=(pa);
ELSIF(a0='1' and a1='1' and ctrreg(1)='1')THEN
internal_bus<=(pb);
ELSIF(a0='0' and a1='1' and st="01")THEN
internal_bus(3 downto 0)<=pcl(3 downto 0);
ELSIF(a0='0' and a1='1' and st="10")THEN
internal_bus(7 downto 0)<=pch(3 downto 0);
ELSIF(a0='0' and a1='1' and st="11" and ctrreg(7)='1')THEN
internal_bus(3 downto 0)<=pcl(3 downto 0);
internal_bus(7 downto 4)<=pch(3 downto 0);
END IF;
ELSE
internal_bus<="ZZZZZZZZ";
END IF;
d<=internal_bus;
END PROCESS;

PROCESS(cs,wr,reset)
BEGIN
IF(cs='0'and wr='0')THEN
ad<=a1&a0;
ctrreg(7)<=d(7);
internal_bus<=d;
END IF;
IF(reset='1')THEN
pa_latch<="00000000";
pb_latch<="00000000";
pc_latch<="00000000";
ctrreg<="10011011";
ELSIF(cs='0' and wr='0')THEN
IF(ctrreg(7)='1' and ad="11" and cs='0')THEN
ctrreg<=internal_bus;
ELSIF(ctrreg(7)='1' and cs='0' and ad="00")THEN
pa_latch<=internal_bus;
ELSIF(ctrreg(7)='1' and cs='0' and ad="01")THEN
pb_latch<=internal_bus;
ELSIF(ctrreg(7)='1' and cs='0' and ad="10")THEN
pc_latch<=internal_bus;
ELSIF(ctrreg(7)='0' and cs='0' and ad="11")THEN
ctrreg(3 downto 0)<=internal_bus(3 downto 0);
CASE ctrreg(3 downto 0) IS
WHEN"0000"=>pc_latch(0)<='0';
WHEN"0010"=>pc_latch(1)<='0';
WHEN"0100"=>pc_latch(2)<='0';
WHEN"0110"=>pc_latch(3)<='0';
WHEN"1000"=>pc_latch(4)<='0';
WHEN"1010"=>pc_latch(5)<='0';
WHEN"1100"=>pc_latch(6)<='0';
WHEN"1110"=>pc_latch(7)<='0';
WHEN"0001"=>pc_latch(0)<='1';
WHEN"0011"=>pc_latch(1)<='1';
WHEN"0101"=>pc_latch(2)<='1';
WHEN"0111"=>pc_latch(3)<='1';
WHEN"1001"=>pc_latch(4)<='1';
WHEN"1011"=>pc_latch(5)<='1';
WHEN"1101"=>pc_latch(6)<='1';
WHEN"1111"=>pc_latch(7)<='1';
when others=>null;
END CASE;
END IF;
END IF;
END PROCESS;

PROCESS(pa_latch)
BEGIN
IF(ctrreg(4)='0')THEN
pa<=(pa_latch);
ELSE
PA<="ZZZZZZZZ";
END IF;
END PROCESS;

PROCESS(pb_latch)
BEGIN
IF(ctrreg(1)='0')THEN
pb<=(pb_latch);
ELSE
pb<="ZZZZZZZZ";
END IF;
END PROCESS;

PROCESS(pc_latch)
BEGIN
IF(ctrreg(0)='0')THEN
pcl<=pc_latch(3 downto 0);
ELSE
pcl<="ZZZZ";
END IF;
END PROCESS;

PROCESS(pc_latch)
BEGIN
IF(ctrreg(3)='0')THEN
pch<=pc_latch(7 downto 4);
ELSE
pch<="ZZZZ";
END IF;
END PROCESS;
END Behavioral;