vhdl用74163设计19进制加法器 功能和时序仿真出现问题 求大神教

Question

检查没错误，但是功能仿真有结果，时序仿真没有结果
求大神教

代码如下：
library ieee;
use ieee.std_logic_1164.all;
entity Sell is
port ( clk,rst:in std_logic;--clk
A,B: in std_logic;
Y,Z:out std_logic);
end Sell;

architecture struct of Sell is
type state is (S0,S1,S2,S3);
signal S:state;
signal M:std_logic_vector(1 downto 0);
begin
M<=A&B;
process (clk,rst,M)
begin
if rst='1' then
S<=S0;

    elsif (clk'event and clk='1') then 
      case S is 
        when S0 =>
            if (M="01") then
            S<=S1;
            Y<='0';Z<='0';
            elsif (M="10") then
            S<=S2;
            Y<='0';Z<='0';
            else 
            S<=S;
            Y<='0';Z<='0';
            end if;
        when S1 =>
            if (M="01") then 
            S<=S2;
            Y<='0';Z<='0';
            elsif (M="10") then
            S<=S0;
            Y<='1';Z<='0';
            else 
            S<=S;
            end if;
        when S2 => 
            if (M="01") then 
            S<=S0;
            Y<='1';Z<='0';
            elsif (M="10") then
            S<=S0;
            Y<='1';Z<='1';
            else 
            S<=S;
            end if;
        when others => 
            S<=S0;
        end case;
    end if;
end process;

end struct;

Answer 1

http://zhangzhenzhen2009.blog.163.com/blog/static/187039247201142682327965/