coldmoodad 2021-07-07 08:33 采纳率: 0%
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有大姥现在看一下这个VHDL改怎么写吗,有偿

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  • 梦幻编织者 2023-06-07 17:28
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    以下是按键连击电路的VHDL代码:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;
    
    entity button_counter is
        Port ( clk : in STD_LOGIC;
               button : in STD_LOGIC;
               reset : in STD_LOGIC;
               digit_out : out STD_LOGIC_VECTOR (3 downto 0);
               segment_out : out STD_LOGIC_VECTOR (6 downto 0));
    end button_counter;
    
    architecture Behavioral of button_counter is
    
        signal counter : unsigned(7 downto 0) := (others => '0');
        signal prev_button : std_logic := '0';
        signal count_enable : std_logic := '0';
        signal count_ended : std_logic := '0';
        signal clock_count : unsigned(23 downto 0) := (others => '0');
    
    begin
    
        -- Clock divider
        process(clk)
        begin
            if rising_edge(clk) then
                if clock_count = 24999999 then
                    clock_count <= (others => '0');
                    count_ended <= '1';
                else
                    clock_count <= clock_count + 1;
                    count_ended <= '0';
                end if;
            end if;
        end process;
    
        -- Button counter
        process(clk, reset)
        begin
            if reset = '1' then
                counter <= (others => '0');
                prev_button <= '0';
                count_enable <= '0';
            elsif rising_edge(clk) then
                if button = '1' and prev_button = '0' then
                    count_enable <= '1';
                    prev_button <= '1';
                else
                    count_enable <= '0';
                    prev_button <= button;
                end if;
    
                if count_enable = '1' then
                    counter <= counter + 1;
                end if;
            end if;
        end process;
    
        -- Display driver
        process(counter, count_ended)
            variable temp : unsigned(7 downto 0);
        begin
            if count_ended = '1' then
                temp := (others => '0');
            else
                temp := counter;
            end if;
    
            case temp is
                when "00000000" =>
                    digit_out <= "1111";
                    segment_out <= "0000001";
                when "00000001" =>
                    digit_out <= "1110";
                    segment_out <= "1001111";
                when "00000010" =>
                    digit_out <= "1101";
                    segment_out <= "0010010";
                when "00000011" =>
                    digit_out <= "1100";
                    segment_out <= "0000110";
                when "00000100" =>
                    digit_out <= "1011";
                    segment_out <= "1001100";
                when "00000101" =>
                    digit_out <= "1010";
                    segment_out <= "0100100";
                when "00000110" =>
                    digit_out <= "1001";
                    segment_out <= "0100000";
                when "00000111" =>
                    digit_out <= "1000";
                    segment_out <= "0001111";
                when "00001000" =>
                    digit_out <= "0111";
                    segment_out <= "0000000";
                when "00001001" =>
                    digit_out <= "0110";
                    segment_out <= "0000100";
                when "00001010" =>
                    digit_out <= "0101";
                    segment_out <= "0001000";
                when "00001011" =>
                    digit_out <= "0100";
                    segment_out <= "1100000";
                when "00001100" =>
                    digit_out <= "0011";
                    segment_out <= "0110001";
                when "00001101" =>
                    digit_out <= "0010";
                    segment_out <= "1000010";
                when "00001110" =>
                    digit_out <= "0001";
                    segment_out <= "0110000";
                when "00001111" =>
                    digit_out <= "0000";
                    segment_out <= "0111000";
                when others =>
                    digit_out <= "1111";
                    segment_out <= "1111111";
            end case;
        end process;
    
    end Behavioral;
    

    该电路包含一个时钟分频器,一个按键计数器和一个数码管显示驱动器。时钟分频器将输入时钟分频为1秒,按键计数器在每次按键时增加计数器的值,数码管显示驱动器将计数器的值转换为七段数码管的显示。
    以下是按键连击电路的测试台代码:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    
    entity button_counter_tb is
    end button_counter_tb;
    
    architecture Behavioral of button_counter_tb is
    
        component button_counter is
            Port ( clk : in STD_LOGIC;
                   button : in STD_LOGIC;
                   reset : in STD_LOGIC;
                   digit_out : out STD_LOGIC_VECTOR (3 downto 0);
                   segment_out : out STD_LOGIC_VECTOR (6 downto 0));
        end component;
    
        signal clk : std_logic := '0';
        signal button : std_logic := '0';
        signal reset : std_logic := '0';
        signal digit_out : std_logic_vector(3 downto 0);
        signal segment_out : std_logic_vector(6 downto 0);
    
    begin
    
        uut: button_counter
            port map (clk, button, reset, digit_out, segment_out);
    
        clk_process : process
        begin
            clk <= '0';
            wait for 10 ns;
            clk <= '1';
            wait for 10 ns;
        end process;
    
        reset_process : process
        begin
            reset <= '1';
            wait for 5 ns;
            reset <= '0';
            wait for 100 ns;
            reset <= '1';
            wait;
        end process;
    
        button_process : process
        begin
            button <= '0';
            wait for 50 ns;
            button <= '1';
            wait for 10 ns;
            button <= '0';
            wait for 20 ns;
            button <= '1';
            wait for 30 ns;
            button <= '0';
            wait for 60 ns;
            button <= '1';
            wait for 40 ns;
            button <= '0';
            wait for 70 ns;
            button <= '1';
            wait for 80 ns;
            button <= '0';
            wait for 90 ns;
            button <= '1';
            wait for 100 ns;
            button <= '0';
            wait for 150 ns;
            button <= '1';
            wait for 200 ns;
            button <= '0';
            wait;
        end process;
    
    end Behavioral;
    

    该测试台代码生成一个时钟信号和一系列模拟按键按下的事件。在仿真中,可以观察到计数器的值随着按键的按下而增加,并在每秒钟重置。数码管显示也会更新以显示当前计数器的值。

    评论

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