vivado与modelsim联合仿真报错。

Question

请问，vivado单独仿真一切正常，vivado与modelsim联合仿真就会报错，报错如下，请问如何解决？
ERROR: [USF-ModelSim-70] 'compile' step failed with error(s) while executing 'D:/FPGA/project/dds1/dds1.sim/sim_1/synth/timing/modelsim/compile.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1669.707 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.