Vivado，遇见多驱动错误与警告怎么修改

Question

问题遇到的现象和发生背景

Vivado在综合工程时出现错误，[Synth 8-4485] pin switch[7] is connected to multiply driven net where other driver is constant
以及警告，[Synth 8-6859] multi-driven net on pin RsData[8] with 1st driver pin 'regf1/__31/out0[8]' ["D:/vivado/project_IO/project_IO.srcs/sources_1/new/regFile.v":37]，应该是RsData多驱动的问题，但是刚接触不知道如何修改，希望指点

问题相关代码，请勿粘贴截图

module LED_switch(
input iow,
input clk,
input a,
input [31:0] DataIn,
output [31:0] Dataout,
input [7:0] switch0,
input [7:0] switch1,
output [7:0] led0,
output [7:0] led1
);

assign Dataout=(a==1'b0)?{24'h0,switch0}:{24'h0,switch1};
reg[7:0] regled[1:0];
assign led0=regled[0];
assign led1=regled[1];

always @(negedge clk)
begin
if(iow)
   if(a==0)
       regled[0]<=DataIn[7:0];
   else
       regled[1]<=DataIn[7:0];
end

endmodule

module regFile(
input clk,
input reset,
input [4:0] RsAddr,
input [4:0] RtAddr,
input [4:0] WriteAddr,
input [31:0] WriteData,
input regwr,
output [31:0] RsData,
output [31:0] RtData

); 
reg[31:0] regs[0:31];//
assign RsData=(RsAddr==5'b0)?32'h0:regs[RsAddr];
assign RtData=(RtAddr==5'b0)?32'h0:regs[RtAddr];
integer i;
always@(negedge clk or posedge reset)
 if(reset)
    for(i=1;i<32;i=i+1)
        regs[i]<=0;
 else if (regwr)
        regs[WriteAddr]<=WriteData;

endmodule
module top(
input clk,
input reset_ext,
input [15:0] switch,
output [15:0] led
);

reg[31:0]  PC;
wire J,B,RegDst,RegWr,ALUSrc,zero,Mem2Reg,MemWr,Bzero;//控制信号
wire [1:0] ALUop;
wire [3:0] ALUctr;
wire [31:0] Instr,RtData,RsData,in2,res,Dataout,WriteData;
wire [31:0] NewPC,JMPC,BPC,NotJMMPC,BranPC,TempPC,Imm32,ImmL2;
wire [4:0]WriteAddr;

wire iow,memw;
wire [31:0] IODataout,memDataout;
wire reset;
  
assign Imm32={{16{Instr[15]}},Instr[15:0]};
assign WriteAddr=RegDst?Instr[15:11]:Instr[20:16];
assign in2=ALUSrc?Instr[15:0]:RtData;
assign WriteData=Mem2Reg?Dataout:res;
assign NotJMMPC=Bzero?BranPC:NewPC;
assign TempPC=J?JMPC:BranPC;
assign Bzero=B&zero;
assign NewPC=PC+4;
assign ImmL2=ALUSrc<<2;
assign JMPC={NewPC[31:28],Instr[25:0],2'b00};
assign BranPC=NewPC+ImmL2;

assign memw=~res[7]&MemWr;
assign iow=res[7]&MemWr;
assign Dataout=res[7]?IODataout:memDataout;
assign reset=~reset_ext;
    
always @(posedge clk)
     if(!reset)
        PC=TempPC;
     else
        PC=32'b0;
mainctr mainctr1(Instr[31:26],ALUop,RegDst,RegWr,ALUSrc,MemWr,B,J,Mem2Reg);
ALU alu(RsData,zero,res,ALUctr,in2);
regFile regf1(clk,reset,Instr[25:21],Instr[20:16],WriteAddr,WriteData,RsData,RtData);
DataRAM dram(.a(res[7:2]),.d(RtData),.clk(!clk),.spo(memDataout),.we(memw));
InstrROM irom(.a(PC[8:2]),.spo(Instr));
LED_switch ledio(clk,iow,IODataout,res[2],RtData,switch[7:0],switch[15:8],led[7:0],led[15:8]);

endmodule

Answer 1

你仔细对比着看 LED_switch 例化的代码和模块代码的引脚顺序和定义
1:clk,iow 好像反了
2:IODataout,a 这俩位宽好像不匹配
3:RtData,Dataout 这俩都是输出(regFile 模块中 RtData 输出)

LED_switch ledio(clk,iow,IODataout,res[2],RtData,switch[7:0],switch[15:8],led[7:0],led[15:8]);

module LED_switch(
input iow,
input clk,
input a,
input [31:0] DataIn,
output [31:0] Dataout,
input [7:0] switch0,
input [7:0] switch1,
output [7:0] led0,
output [7:0] led1
)