VHDL程序显示 "work" 明天包含"register_stage"要怎么解决？

Question

代码是在GitHub上找到的，编译后出现这个报错，
错误：Error (10481): VHDL Use Clause error at qarma.vhd(383): design library "work" does not contain primary unit "register_stage"

代码如下，报错显示位置在下方第一行

**internal_reg : entity work.register_stage**
    generic map(
      WIDTH      => 64,
      REGISTERED => true
      )
    port map(
      clk    => ClkxCI,
      resetn => RstxRBI,

      in_data  => RegisterInxD,
      in_valid => RegisterInValidxS,
      in_ready => RegisterInReadyxS,

      out_data  => RegisterOutxD,
      out_valid => RegisterOutValidxS,
      out_ready => RegisterOutReadyxS
      );

  rounds_1 : for r in 0 to ROUNDS-2 generate
    State1xD(r+1) <= ROUND_INV(State1xD(r), K0xD xor TweakxD(ROUNDS-1-r) xor RoundConstxD(ROUNDS-1-r) xor AlphaxD);
  end generate rounds_1;

  State1xD(ROUNDS) <= ROUND_INV_SHORT(State1xD(ROUNDS-1), K0xD xor TweakxD(0) xor RoundConstxD(0) xor AlphaxD);

  CiphertextxDO <= State1xD(ROUNDS) xor W1xD;
end Behavioral;