VHDL语言怎么处理这个问题，求解答

Question

各位，这里我想用VHDL语言来实现，中间变量怎么处理呢？
以下是我的代码，希望各位求解。

library ieee;
use ieee.std_logic_1164.all;
entity d is
port(a,b,enable:in std_logic_1164;
   z0,z1,z2,z3: out std_logic_1164);
    
end d;
architecture qimo of dzl is
signal x,y:std_logic;

begin
process(a,b,enable) 
            x <= not a;
            y <= not b;
z0<= enable nand x nand y;
z1<= enable nand x nand b;
z2<= enable nand a nand y;
z3<= enable nand a nand b;
end qimo